» DVM Test Report Overview

General
Schematic LTC3406B - DVM ADVANCED.sxsch
Testplan dvm_advanced.testplan
Original Testplan Filename dvm_builtin-syncbuck_1in_1out.testplan
Date / Time 2013-04-17 10:02:01 AM
Report Directory DVM_REPORTS\2013-04-17-10_02_00_AM
Log File dvm_advanced.log
# of Tests Run 6 of 6 (6 of 6 Run, 5 Passed, 1 Failed, 0 Ran with Warnings, 0 Skipped)
Total Time 31s
Design Specifications
Circuit Name LTC3406B
Description Synchronous Buck
Input 1 5.000 V (4.5 V to 5.5 V)
Output 1 1.505 V (±5%) @ 1.5 A
Switching Frequency 955kHz
Excel-compatible Results
Scalar Results dvm_advanced_table_scalars.txt
Spec Results dvm_advanced_table_specs.txt
Test 1 of 6top ^
Test Label Ac Analysis|Bode Plot|Vin Nominal|Light Load
Simulator simplis
Test Report Ac Analysis\Bode Plot\Vin Nominal\Light Load\report.txt.html
Status FAIL
Test Time 5s
Test 2 of 6top ^
Test Label Ac Analysis|Bode Plot|Vin Nominal|50% Load
Simulator simplis
Test Report Ac Analysis\Bode Plot\Vin Nominal\50% Load\report.txt.html
Status PASS
Test Time 5s
Test 3 of 6top ^
Test Label Ac Analysis|Bode Plot|Vin Nominal|100% Load
Simulator simplis
Test Report Ac Analysis\Bode Plot\Vin Nominal\100% Load\report.txt.html
Status PASS
Test Time 5s
Test 4 of 6top ^
Test Label Steady-State|Steady-State|Vin Nominal|Light Load
Simulator simplis
Test Report Steady-State\Steady-State\Vin Nominal\Light Load\report.txt.html
Status PASS
Test Time 3s
Test 5 of 6top ^
Test Label Steady-State|Steady-State|Vin Nominal|50% Load
Simulator simplis
Test Report Steady-State\Steady-State\Vin Nominal\50% Load\report.txt.html
Status PASS
Test Time 3s
Test 6 of 6top ^
Test Label Steady-State|Steady-State|Vin Nominal|100% Load
Simulator simplis
Test Report Steady-State\Steady-State\Vin Nominal\100% Load\report.txt.html
Status PASS
Test Time 3s