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» DVM Test Report: Steady-State|Steady-State|Vin Minimum|80%

Test Details
Schematic 4.2_LTC3406B - DVM ADVANCED.sxsch
Test Steady-State|Steady-State|Vin Minimum|80%
Date / Time 4/18/2013 11:01:43 AM
Report Directory DVM_REPORTS\2013-04-18-10_58_35_AM\Steady-State\Steady-State\Vin Minimum\80%
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 71.0966%
Efficiency_Min 71.0966%
Frequency(CLK) 955.63983kHertz
Power(LOAD123) 1.80733
Power(SRC) 2.54207
ILOAD123
AVG
1.20044
MIN
1.1976
MAX
1.20316
RMS
1.20044
ILOUT
AVG
1.20044
MIN
934.732m
MAX
1.46748
RMS
1.21026
ISRC
AVG
565.058m
MIN
381.279u
MAX
1.46786
RMS
832.177m
SW
AVG
1.62559
MIN
-1.28699
MAX
4.12503
RMS
2.77074
VLOAD123
AVG
1.50555
MIN
1.50199
MAX
1.50896
RMS
1.50555
PK2PK
6.97395m
VOUT
AVG
1.50555
MIN
1.50199
MAX
1.50896
RMS
1.50555
VSRC
AVG
4.49943
MIN
4.49853
MAX
4.5
RMS
4.49943
Measured Spec Values
Max_VLOAD123 PASS: Max. Output1 Voltage (1.50896) is less than or equal to Max. Output1 Voltage Spec (1.58025)
Min_VLOAD123 PASS: Min. Output1 Voltage (1.50199) is greater than or equal to Min. Output1 Voltage Spec (1.42975)
LOAD123
VLOAD123
ILOAD123
SXGPH File simplis_pop84_2948.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop84_2938.sxgph
default
CLK
ILOUT
SW
VOUT
SXGPH File simplis_pop84_2943.sxgph
Other SXGPH Files
clock#pop simplis_pop84_2930.sxgph