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» DVM Test Report: Steady-State|Input 1 Maximum Voltage, Output 1 Light Load

Test Details
Schematic 5.1_LTC3406B - DVM ADVANCED.sxsch
Test Steady-State|Input 1 Maximum Voltage, Output 1 Light Load
Date / Time 4/18/2013 1:12:45 PM
Report Directory DVM_REPORTS\2013-04-18-1_12_37_PM\Steady-State\Input 1 Maximum Voltage, Output 1 Light Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 91.4346%
Frequency(CLK) 955.70285kHertz
Power(LOAD) 75.3274m
Power(SRC) 82.3839m
ILOAD
AVG
50.0271m
MIN
49.9701m
MAX
50.0766m
RMS
50.0271m
ILOUT
AVG
50.0271m
MIN
-122.942u
MAX
231.665m
RMS
87.7364m
ISRC
AVG
14.9793m
MIN
349.963u
MAX
550.21m
RMS
47.6919m
SW
AVG
1.51085
MIN
-792.663m
MAX
6.20005
RMS
2.22769
VLOAD
AVG
1.50573
MIN
1.50402
MAX
1.50722
RMS
1.50573
PK2PK
3.20748m
VOUT
AVG
1.50573
MIN
1.50402
MAX
1.50722
RMS
1.50573
VSRC
AVG
5.49999
MIN
5.49945
MAX
5.5
RMS
5.49999
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (1.50722) is less than or equal to Max. Output1 Voltage Spec (1.58025)
Min_VLOAD PASS: Min. Output1 Voltage (1.50402) is greater than or equal to Min. Output1 Voltage Spec (1.42975)
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop2_54.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop2_44.sxgph
default
CLK
ILOUT
SW
VOUT
SXGPH File simplis_pop2_49.sxgph
Other SXGPH Files
clock#pop simplis_pop2_36.sxgph