* SCHEMATIC : ..\..\5.1_LTC3406B - DVM ADVANCED.sxsch
* TESTPLAN : dvm_advanced.testplan
* ORIGINALTP: line_and_load_regulation.testplan
* DATE : 2013-04-18
* TIME : 1:12:37 PM
* REPORT DIR: D:\simplistechnologies.com\website\documentation\dvmtutorial\LTC3406B\Test Ckts\DVM_REPORTS\2013-04-18-1_12_37_PM
* NUM TESTS : 7
*
*
* TEST : Steady-State|Input 1 Minimum Voltage, Output 1 100% Load
* PROGRESS : 1 of 7
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\simplistechnologies.com\website\documentation\dvmtutorial\LTC3406B\Test Ckts\DVM_REPORTS\2013-04-18-1_12_37_PM\Steady-State\Input 1 Minimum Voltage, Output 1 100% Load/report.txt
* DECK : Steady-State\Input 1 Minimum Voltage, Output 1 100% Load\input.deck
* INIT : Steady-State\Input 1 Minimum Voltage, Output 1 100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Input 1 Minimum Voltage, Output 1 100% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Steady-State|Input 1 Maximum Voltage, Output 1 Light Load
* PROGRESS : 2 of 7
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\simplistechnologies.com\website\documentation\dvmtutorial\LTC3406B\Test Ckts\DVM_REPORTS\2013-04-18-1_12_37_PM\Steady-State\Input 1 Maximum Voltage, Output 1 Light Load/report.txt
* DECK : Steady-State\Input 1 Maximum Voltage, Output 1 Light Load\input.deck
* INIT : Steady-State\Input 1 Maximum Voltage, Output 1 Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Input 1 Maximum Voltage, Output 1 Light Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Steady-State|Input 1 Nominal Voltage, Output 1 100% Load
* PROGRESS : 3 of 7
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\simplistechnologies.com\website\documentation\dvmtutorial\LTC3406B\Test Ckts\DVM_REPORTS\2013-04-18-1_12_37_PM\Steady-State\Input 1 Nominal Voltage, Output 1 100% Load/report.txt
* DECK : Steady-State\Input 1 Nominal Voltage, Output 1 100% Load\input.deck
* INIT : Steady-State\Input 1 Nominal Voltage, Output 1 100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Input 1 Nominal Voltage, Output 1 100% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Steady-State|Input 1 Nominal Voltage, Output 1 Light Load
* PROGRESS : 4 of 7
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\simplistechnologies.com\website\documentation\dvmtutorial\LTC3406B\Test Ckts\DVM_REPORTS\2013-04-18-1_12_37_PM\Steady-State\Input 1 Nominal Voltage, Output 1 Light Load/report.txt
* DECK : Steady-State\Input 1 Nominal Voltage, Output 1 Light Load\input.deck
* INIT : Steady-State\Input 1 Nominal Voltage, Output 1 Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Input 1 Nominal Voltage, Output 1 Light Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Steady-State|Input 1 Minimum Voltage, Output 1 50% Load
* PROGRESS : 5 of 7
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\simplistechnologies.com\website\documentation\dvmtutorial\LTC3406B\Test Ckts\DVM_REPORTS\2013-04-18-1_12_37_PM\Steady-State\Input 1 Minimum Voltage, Output 1 50% Load/report.txt
* DECK : Steady-State\Input 1 Minimum Voltage, Output 1 50% Load\input.deck
* INIT : Steady-State\Input 1 Minimum Voltage, Output 1 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Input 1 Minimum Voltage, Output 1 50% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Steady-State|Input 1 Maximum Voltage, Output 1 50% Load
* PROGRESS : 6 of 7
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\simplistechnologies.com\website\documentation\dvmtutorial\LTC3406B\Test Ckts\DVM_REPORTS\2013-04-18-1_12_37_PM\Steady-State\Input 1 Maximum Voltage, Output 1 50% Load/report.txt
* DECK : Steady-State\Input 1 Maximum Voltage, Output 1 50% Load\input.deck
* INIT : Steady-State\Input 1 Maximum Voltage, Output 1 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Input 1 Maximum Voltage, Output 1 50% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Final Math
* PROGRESS : 7 of 7
* SIMULATOR : simplis
* LOG : D:\simplistechnologies.com\website\documentation\dvmtutorial\LTC3406B\Test Ckts\DVM_REPORTS\2013-04-18-1_12_37_PM\Final Math/report.txt
* SIMULATOR : N/A
* STATUS : SKIP
* RESULT : Line and Load Regulation (Input 1, Output 1)=3.7136213%
* RESULT : Load Regulation (Output 1) for Output 1=0.0079734219%
* RESULT : Line Regulation (Input 1) for Output 1=0.0059800664%
* EXECUTED : simplis_dvm_advanced_testplan_line_and_load_regulation_post_process, returned 0 scalars, 0 specs.
* RSTATUS : SKIP
* REPORT : D:\simplistechnologies.com\website\documentation\dvmtutorial\LTC3406B\Test Ckts\DVM_REPORTS\2013-04-18-1_12_37_PM\Final Math/report.txt
* TEST TIME : 1 seconds
*
*
* TOTAL TIME: 31 seconds
* TESTS RUN : 7 of 7