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» DVM Test Report: VOUT=0.6V w NoCurves NoScalars NoSpecs|Bode Plot|Vin Maximum|50% Load

Test Details
Schematic 6.3_LTC3406B - DVM ADVANCED.sxsch
Test VOUT=0.6V w NoCurves NoScalars NoSpecs|Bode Plot|Vin Maximum|50% Load
Date / Time 4/25/2013 8:29:08 AM
Report Directory DVM_REPORTS\2013-04-25-8_28_49_AM\VOUT=0.6V w NoCurves NoScalars NoSpecs\Bode Plot\Vin Maximum\50% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 76.7746%
Frequency(CLK) 955.69661kHertz
Power(LOAD) 182.683m
Power(SRC) 237.946m
gain_crossover_freq 19.9547k
gain_margin 33.8124
min_phase 39.869
phase_crossover_freq 335.599k
min_phase_freq 19.9547k
phase_margin 39.8688
ILOUT
AVG
301.724m
MIN
118.808m
MAX
497.963m
RMS
320.972m
SW
AVG
635.632m
MIN
-899.182m
MAX
5.45209
RMS
1.99744
VLOAD
AVG
605.46m
MIN
602.998m
MAX
606.966m
RMS
605.461m
VOUT
AVG
605.46m
MIN
602.998m
MAX
606.966m
RMS
605.461m
Measured Spec Values
min_gain_margin PASS: Gain Margin (33.8124) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (39.8688) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac3_130.sxgph
LOAD
VLOAD
SXGPH File simplis_pop3_113.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop3_103.sxgph
default
CLK
ILOUT
SW
VOUT
SXGPH File simplis_pop3_108.sxgph
Other SXGPH Files
DVM Bode Plot Input#log#ac simplis_ac3_137.sxgph
clock#pop simplis_pop3_95.sxgph