Test Details | |
Schematic | 6.3_LTC3406B - DVM ADVANCED.sxsch |
Test | VOUT=1.505V|Bode Plot|Vin Nominal|50% Load |
Date / Time | 4/25/2013 8:28:57 AM |
Report Directory | DVM_REPORTS\2013-04-25-8_28_49_AM\VOUT=1.505V\Bode Plot\Vin Nominal\50% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 78.7659% |
Frequency(CLK) | 955.65066kHertz |
Power(LOAD) | 1.12969 |
Power(SRC) | 1.43424 |
gain_crossover_freq | 20.8851k |
gain_margin | 30.3822 |
min_phase | 37.0236 |
phase_crossover_freq | 398.963k |
min_phase_freq | 20.8851k |
phase_margin | 36.9764 |
ILOAD | AVG 750.312m MIN 748.387m MAX 751.945m RMS 750.313m |
ILOUT | AVG 750.312m MIN 413.589m MAX 1.09521 RMS 775.722m |
ISRC | AVG 286.895m MIN 423.445u MAX 1.09563 RMS 482.345m |
SW | AVG 1.58066 MIN -1.13808 MAX 4.83389 RMS 2.89056 |
VLOAD | AVG 1.50562 MIN 1.50176 MAX 1.5089 RMS 1.50563 |
VOUT | AVG 1.50562 MIN 1.50176 MAX 1.5089 RMS 1.50563 |
VSRC | AVG 4.99971 MIN 4.9989 MAX 5 RMS 4.99971 |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (1.5089) is less than or equal to Max. Output1 Voltage Spec (1.58025) |
Min_VLOAD | PASS: Min. Output1 Voltage (1.50176) is greater than or equal to Min. Output1 Voltage Spec (1.42975) |
min_gain_margin | PASS: Gain Margin (30.3822) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (36.9764) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac1_36.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop1_19.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop1_9.sxgph |
default
CLK
ILOUT
SW
VOUT
|
|
SXGPH File | simplis_pop1_14.sxgph |
Other SXGPH Files | |
clock#pop | simplis_pop1_1.sxgph |
DVM Bode Plot Input#log#ac | simplis_ac1_43.sxgph |