» DVM Test Report Overview

General
Schematic 6.5.1_LTC3406B - DVM ADVANCED.sxsch
Testplan dvm_advanced.testplan
Original Testplan Filename 6.5.1_arbitrary_curve_final.testplan
Date / Time 2013-04-25 9:28:02 AM
Report Directory DVM_REPORTS\2013-04-25-9_27_57_AM
Log File dvm_advanced.log
# of Tests Run 1 of 1 (All Pass)
Total Time 5s
Design Specifications
Circuit Name LTC3406B
Description Synchronous Buck
Input 1 5.000 V (4.5 V to 5.5 V)
Output 1 1.505 V (±5%) @ 1.5 A
Switching Frequency 955kHz
Excel-compatible Results
Scalar Results dvm_advanced_table_scalars.txt
Spec Results dvm_advanced_table_specs.txt
Test 1 of 1top ^
Test Label Steady-State|Steady-State|Vin Maximum|100% Load
Simulator simplis
Test Report Steady-State\Steady-State\Vin Maximum\100% Load\report.txt.html
Status PASS
Test Time 4s