SystemDesigner

SystemDesigner Mux - 2, 3, and 4 Input

The SystemDesigner Mux models a selection multiplexer with two to four SystemDesigner bus inputs and a 32-bit signed-integer or floating-point result. From the Output parameter box, you can limit the resulting output to either signed or unsigned numbers with fewer than 32 bits.

The propagation delay can be defined as a fixed time, as asynchronous to any clock, or as a synchronous delay where the delay is a number of SystemDesigner-clocks cycles. In this release of SystemDesigner, the synchronous delay is supported only for integer-sampled data simulations.

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Model Name:

  • SystemDesigner MUX - 2 Inputs
  • SystemDesigner MUX - 3 Input
  • SystemDesigner MUX - 4 Inputs

Simulator:

This device is compatible with the SIMPLIS simulator.

Parts Selector
Menu Location:

SystemDesigner Functions (max. 32 bit) | Muxes

Symbol Library:

SIMPLIS_SystemDesigner.sxslb

Model File:

SIMPLIS_SystemDesigner.lb

Subcircuit Name:

  • SIMPLIS_SD_MUX_32_X_2
  • SIMPLIS_SD_MUX_32_X_3
  • SIMPLIS_SD_MUX_32_X_4

Symbols:

  

Multiple Selections:

Only one device at a time can be edited.

Editing the Mux

To configure the Mux, double click the symbol to open the parameter editing dialog.

Label Parameter Description

Use asynchronous delay

Implements a combinatorial model where the output voltage changes in response to the input voltage(s) change after a propagation delay.

Propagation Delay

The propagation delay from an input change to an output change in seconds.
This parameter is used only in models with Asynchronous delay.

Use synchronous delay

In response to an input voltage change, the output voltage changes after a designated number of clock cycles.

Delay

The propagation delay from an input change to an output change in number of clock cycles. The output will not change until the number of clock cycles has been reached. The output will then change state only on the selected Clock source edges specified by Trigger edge.
The Clock source can be set using the SystemDesigner->Edit SystemDesigner Clocks... menu item.
This parameter is used only in models with Synchronous delay.

Clock source

Specifies the global clock used for the Synchronous delay block.
The Clock source can be set using the SystemDesigner->Edit SystemDesigner Clocks... menu item.
This parameter is used only in models with Synchronous delay.

Trigger edge

Sets the output to change on specific edges of the Clock source :

  • 0_TO_1 The output changes only on rising edges of the Clock source
  • 1_TO_0 The output changes only on falling edges of the Clock source
This parameter is used only in models with Synchronous delay.

Use 32 bit signed

The full 32-bit signed data is output.

Limit output to:

The output is limited to a Signed or Unsigned number with a designated number of bits.

Number type

The output will be limited to either a Signed or Unsigned number if Limit output to is selected.

  • Signed numbers include integers from -2Number of bits-1 to 2Number of bits-1-1
  • Unsigned numbers include integers from 0 to 2Number of bits
This parameter is used only in models with Limit output to selected.

Number of bits

The limit on the output depends on the Number type parameter :

  • Signed numbers include integers from -2Number of bits-1 to 2Number of bits-1-1
  • Unsigned numbers include integers from 0 to 2Number of bits
This parameter is used only in models with Limit output to selected.

Initial Condition

Initial condition of the output at time=0. Value is the output bus represented in decimal format.

Examples

The gain selection circuit using a 3-input Mux can be downloaded here: simplis_117_systemdesigner_mux_3_example.zip. In order to simulate this design, follow these steps:

  1. If you currently have a dialog box open in SIMetrix/SIMPLIS, cancel that dialog box so that the example can open in SIMetrix/SIMPLIS.
  2. Unzip the archive to a location on your computer.
  3. To open the schematic, double click the .sxsch file or drag that file into the SIMetrix/SIMPLIS Command Shell.

Waveforms

The circuit example below uses a Mux to select from three gain values, 1, 2, or 4. The Input voltage to the ADC is a sine wave with the following parameters:

The ADC output has a peak value of +/- 3 LSB counts. This peak value is gained by the three gain blocks, and then the 3-input Mux selects one of the gained values to output.

The counter used in this example is a conventional SIMPLIS up-type counter; as such, the output bus from the counter is only two bits wide. A bus ripper is used to connect the counter to the Select input of the Mux. The selection of the inputs is decoded as follows:

Select Input in Decimal Input Selected

0

I0

1

I1

2

I2

3

I2

The clock input of the counter is defined in the SystemDesigner Clocks dialog and appears on the schematic using the SystemDesigner Global Clock Breakout device. The clock has a 40us delay and the same frequency as the sine wave input source to the ADC, which is 25kHz.

If you intend to use a gain-selection circuit similar to this example, make certain that the selection bus is constant for floating-point simulations because switching gain during a POP simulation causes the POP to fail to converge. In this example, the counter output is 0 for the POP and AC simulations; as such, the Mux selection will be I0, and the AC gain from the sampled data to the output of the Mux will be 0 dB because that is the gain of the I0 path of the Mux. If you change the initial condition of the counter to 1 or 2, you will see the gain change to 6dB and 12dB ,respectively.

The AC transfer function for the Mux is shown below. Note that the axis scales are fempto Degrees and fempto dB.

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