* SCHEMATIC : ..\..\LTC3406B - DVM ADVANCED.sxsch
* TESTPLAN : dvm_advanced.testplan
* DATE : 2011-05-23
* TIME : 15:12:10 PM
* REPORT DIR: D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM
* NUM TESTS : 129
*
*
* TEST : Ac Analysis|Bode Plot|Vin Nominal|Light Load
* PROGRESS : 1 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Bode Plot\Vin Nominal\Light Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Nominal\Light Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Nominal\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Ac Analysis\Bode Plot\Vin Nominal\Light Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Nominal|50% Load
* PROGRESS : 2 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Bode Plot\Vin Nominal\50% Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Nominal\50% Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Nominal\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Bode Plot\Vin Nominal\50% Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Nominal|100% Load
* PROGRESS : 3 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Bode Plot\Vin Nominal\100% Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Nominal\100% Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Nominal\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Bode Plot\Vin Nominal\100% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Minimum|Light Load
* PROGRESS : 4 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Bode Plot\Vin Minimum\Light Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Minimum\Light Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Minimum\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Ac Analysis\Bode Plot\Vin Minimum\Light Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Minimum|50% Load
* PROGRESS : 5 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Bode Plot\Vin Minimum\50% Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Minimum\50% Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Minimum\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Bode Plot\Vin Minimum\50% Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Minimum|100% Load
* PROGRESS : 6 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Bode Plot\Vin Minimum\100% Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Minimum\100% Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Minimum\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : WARN
* REPORT : Ac Analysis\Bode Plot\Vin Minimum\100% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Maximum|Light Load
* PROGRESS : 7 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Bode Plot\Vin Maximum\Light Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Maximum\Light Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Maximum\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Ac Analysis\Bode Plot\Vin Maximum\Light Load\report.txt.html
* TEST TIME : 6 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Maximum|50% Load
* PROGRESS : 8 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Bode Plot\Vin Maximum\50% Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Maximum\50% Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Maximum\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Bode Plot\Vin Maximum\50% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Maximum|100% Load
* PROGRESS : 9 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Bode Plot\Vin Maximum\100% Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Maximum\100% Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Maximum\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Bode Plot\Vin Maximum\100% Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Ac Analysis|Conducted Susceptibility|Vin Nominal|Light Load
* PROGRESS : 10 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Conducted Susceptibility\Vin Nominal\Light Load/report.txt
* DECK : Ac Analysis\Conducted Susceptibility\Vin Nominal\Light Load\input.deck
* INIT : Ac Analysis\Conducted Susceptibility\Vin Nominal\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Conducted Susceptibility\Vin Nominal\Light Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Ac Analysis|Conducted Susceptibility|Vin Nominal|50% Load
* PROGRESS : 11 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Conducted Susceptibility\Vin Nominal\50% Load/report.txt
* DECK : Ac Analysis\Conducted Susceptibility\Vin Nominal\50% Load\input.deck
* INIT : Ac Analysis\Conducted Susceptibility\Vin Nominal\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Conducted Susceptibility\Vin Nominal\50% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Ac Analysis|Conducted Susceptibility|Vin Nominal|100% Load
* PROGRESS : 12 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Conducted Susceptibility\Vin Nominal\100% Load/report.txt
* DECK : Ac Analysis\Conducted Susceptibility\Vin Nominal\100% Load\input.deck
* INIT : Ac Analysis\Conducted Susceptibility\Vin Nominal\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Conducted Susceptibility\Vin Nominal\100% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Conducted Susceptibility|Vin Minimum|Light Load
* PROGRESS : 13 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Conducted Susceptibility\Vin Minimum\Light Load/report.txt
* DECK : Ac Analysis\Conducted Susceptibility\Vin Minimum\Light Load\input.deck
* INIT : Ac Analysis\Conducted Susceptibility\Vin Minimum\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Conducted Susceptibility\Vin Minimum\Light Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Conducted Susceptibility|Vin Minimum|50% Load
* PROGRESS : 14 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Conducted Susceptibility\Vin Minimum\50% Load/report.txt
* DECK : Ac Analysis\Conducted Susceptibility\Vin Minimum\50% Load\input.deck
* INIT : Ac Analysis\Conducted Susceptibility\Vin Minimum\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Conducted Susceptibility\Vin Minimum\50% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Conducted Susceptibility|Vin Minimum|100% Load
* PROGRESS : 15 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Conducted Susceptibility\Vin Minimum\100% Load/report.txt
* DECK : Ac Analysis\Conducted Susceptibility\Vin Minimum\100% Load\input.deck
* INIT : Ac Analysis\Conducted Susceptibility\Vin Minimum\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Conducted Susceptibility\Vin Minimum\100% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Conducted Susceptibility|Vin Maximum|Light Load
* PROGRESS : 16 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Conducted Susceptibility\Vin Maximum\Light Load/report.txt
* DECK : Ac Analysis\Conducted Susceptibility\Vin Maximum\Light Load\input.deck
* INIT : Ac Analysis\Conducted Susceptibility\Vin Maximum\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Conducted Susceptibility\Vin Maximum\Light Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Ac Analysis|Conducted Susceptibility|Vin Maximum|50% Load
* PROGRESS : 17 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Conducted Susceptibility\Vin Maximum\50% Load/report.txt
* DECK : Ac Analysis\Conducted Susceptibility\Vin Maximum\50% Load\input.deck
* INIT : Ac Analysis\Conducted Susceptibility\Vin Maximum\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Conducted Susceptibility\Vin Maximum\50% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Ac Analysis|Conducted Susceptibility|Vin Maximum|100% Load
* PROGRESS : 18 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Conducted Susceptibility\Vin Maximum\100% Load/report.txt
* DECK : Ac Analysis\Conducted Susceptibility\Vin Maximum\100% Load\input.deck
* INIT : Ac Analysis\Conducted Susceptibility\Vin Maximum\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Conducted Susceptibility\Vin Maximum\100% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Input Impedance|Vin Nominal|Light Load
* PROGRESS : 19 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Input Impedance\Vin Nominal\Light Load/report.txt
* DECK : Ac Analysis\Input Impedance\Vin Nominal\Light Load\input.deck
* INIT : Ac Analysis\Input Impedance\Vin Nominal\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Input Impedance\Vin Nominal\Light Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Ac Analysis|Input Impedance|Vin Nominal|50% Load
* PROGRESS : 20 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Input Impedance\Vin Nominal\50% Load/report.txt
* DECK : Ac Analysis\Input Impedance\Vin Nominal\50% Load\input.deck
* INIT : Ac Analysis\Input Impedance\Vin Nominal\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Input Impedance\Vin Nominal\50% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Ac Analysis|Input Impedance|Vin Nominal|100% Load
* PROGRESS : 21 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Input Impedance\Vin Nominal\100% Load/report.txt
* DECK : Ac Analysis\Input Impedance\Vin Nominal\100% Load\input.deck
* INIT : Ac Analysis\Input Impedance\Vin Nominal\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Input Impedance\Vin Nominal\100% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Ac Analysis|Input Impedance|Vin Minimum|Light Load
* PROGRESS : 22 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Input Impedance\Vin Minimum\Light Load/report.txt
* DECK : Ac Analysis\Input Impedance\Vin Minimum\Light Load\input.deck
* INIT : Ac Analysis\Input Impedance\Vin Minimum\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Input Impedance\Vin Minimum\Light Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Input Impedance|Vin Minimum|50% Load
* PROGRESS : 23 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Input Impedance\Vin Minimum\50% Load/report.txt
* DECK : Ac Analysis\Input Impedance\Vin Minimum\50% Load\input.deck
* INIT : Ac Analysis\Input Impedance\Vin Minimum\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Input Impedance\Vin Minimum\50% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Input Impedance|Vin Minimum|100% Load
* PROGRESS : 24 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Input Impedance\Vin Minimum\100% Load/report.txt
* DECK : Ac Analysis\Input Impedance\Vin Minimum\100% Load\input.deck
* INIT : Ac Analysis\Input Impedance\Vin Minimum\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Input Impedance\Vin Minimum\100% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Input Impedance|Vin Maximum|Light Load
* PROGRESS : 25 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Input Impedance\Vin Maximum\Light Load/report.txt
* DECK : Ac Analysis\Input Impedance\Vin Maximum\Light Load\input.deck
* INIT : Ac Analysis\Input Impedance\Vin Maximum\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Input Impedance\Vin Maximum\Light Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Input Impedance|Vin Maximum|50% Load
* PROGRESS : 26 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Input Impedance\Vin Maximum\50% Load/report.txt
* DECK : Ac Analysis\Input Impedance\Vin Maximum\50% Load\input.deck
* INIT : Ac Analysis\Input Impedance\Vin Maximum\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Input Impedance\Vin Maximum\50% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Input Impedance|Vin Maximum|100% Load
* PROGRESS : 27 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Input Impedance\Vin Maximum\100% Load/report.txt
* DECK : Ac Analysis\Input Impedance\Vin Maximum\100% Load\input.deck
* INIT : Ac Analysis\Input Impedance\Vin Maximum\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Input Impedance\Vin Maximum\100% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Output Impedance|Vin Nominal|Light Load
* PROGRESS : 28 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Output Impedance\Vin Nominal\Light Load/report.txt
* DECK : Ac Analysis\Output Impedance\Vin Nominal\Light Load\input.deck
* INIT : Ac Analysis\Output Impedance\Vin Nominal\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Output Impedance\Vin Nominal\Light Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Output Impedance|Vin Nominal|50% Load
* PROGRESS : 29 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Output Impedance\Vin Nominal\50% Load/report.txt
* DECK : Ac Analysis\Output Impedance\Vin Nominal\50% Load\input.deck
* INIT : Ac Analysis\Output Impedance\Vin Nominal\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Output Impedance\Vin Nominal\50% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Output Impedance|Vin Nominal|100% Load
* PROGRESS : 30 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Output Impedance\Vin Nominal\100% Load/report.txt
* DECK : Ac Analysis\Output Impedance\Vin Nominal\100% Load\input.deck
* INIT : Ac Analysis\Output Impedance\Vin Nominal\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Output Impedance\Vin Nominal\100% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Ac Analysis|Output Impedance|Vin Minimum|Light Load
* PROGRESS : 31 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Output Impedance\Vin Minimum\Light Load/report.txt
* DECK : Ac Analysis\Output Impedance\Vin Minimum\Light Load\input.deck
* INIT : Ac Analysis\Output Impedance\Vin Minimum\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Output Impedance\Vin Minimum\Light Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Ac Analysis|Output Impedance|Vin Minimum|50% Load
* PROGRESS : 32 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Output Impedance\Vin Minimum\50% Load/report.txt
* DECK : Ac Analysis\Output Impedance\Vin Minimum\50% Load\input.deck
* INIT : Ac Analysis\Output Impedance\Vin Minimum\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Output Impedance\Vin Minimum\50% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Output Impedance|Vin Minimum|100% Load
* PROGRESS : 33 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Output Impedance\Vin Minimum\100% Load/report.txt
* DECK : Ac Analysis\Output Impedance\Vin Minimum\100% Load\input.deck
* INIT : Ac Analysis\Output Impedance\Vin Minimum\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Output Impedance\Vin Minimum\100% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Ac Analysis|Output Impedance|Vin Maximum|Light Load
* PROGRESS : 34 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Output Impedance\Vin Maximum\Light Load/report.txt
* DECK : Ac Analysis\Output Impedance\Vin Maximum\Light Load\input.deck
* INIT : Ac Analysis\Output Impedance\Vin Maximum\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Output Impedance\Vin Maximum\Light Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Output Impedance|Vin Maximum|50% Load
* PROGRESS : 35 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Output Impedance\Vin Maximum\50% Load/report.txt
* DECK : Ac Analysis\Output Impedance\Vin Maximum\50% Load\input.deck
* INIT : Ac Analysis\Output Impedance\Vin Maximum\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Output Impedance\Vin Maximum\50% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Ac Analysis|Output Impedance|Vin Maximum|100% Load
* PROGRESS : 36 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Ac Analysis\Output Impedance\Vin Maximum\100% Load/report.txt
* DECK : Ac Analysis\Output Impedance\Vin Maximum\100% Load\input.deck
* INIT : Ac Analysis\Output Impedance\Vin Maximum\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Output Impedance\Vin Maximum\100% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Nominal|Light Load to 25% Load
* PROGRESS : 37 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\Light Load to 25% Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\Light Load to 25% Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\Light Load to 25% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\Light Load to 25% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Nominal|Light Load to 50% Load
* PROGRESS : 38 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\Light Load to 50% Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\Light Load to 50% Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\Light Load to 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\Light Load to 50% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Nominal|Light Load to 100% Load
* PROGRESS : 39 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\Light Load to 100% Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\Light Load to 100% Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\Light Load to 100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\Light Load to 100% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Load|Vin Nominal|25% Load to Light Load
* PROGRESS : 40 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\25% Load to Light Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\25% Load to Light Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\25% Load to Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\25% Load to Light Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Step Load|Vin Nominal|25% Load to 50% Load
* PROGRESS : 41 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\25% Load to 50% Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\25% Load to 50% Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\25% Load to 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\25% Load to 50% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Load|Vin Nominal|50% Load to Light Load
* PROGRESS : 42 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\50% Load to Light Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\50% Load to Light Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\50% Load to Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\50% Load to Light Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Step Load|Vin Nominal|50% Load to 25% Load
* PROGRESS : 43 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\50% Load to 25% Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\50% Load to 25% Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\50% Load to 25% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\50% Load to 25% Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Step Load|Vin Nominal|50% Load to 75% Load
* PROGRESS : 44 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\50% Load to 75% Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\50% Load to 75% Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\50% Load to 75% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\50% Load to 75% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Load|Vin Nominal|50% Load to 100% Load
* PROGRESS : 45 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\50% Load to 100% Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\50% Load to 100% Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\50% Load to 100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\50% Load to 100% Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Step Load|Vin Nominal|75% Load to 100% Load
* PROGRESS : 46 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\75% Load to 100% Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\75% Load to 100% Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\75% Load to 100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\75% Load to 100% Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Step Load|Vin Nominal|75% Load to 50% Load
* PROGRESS : 47 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\75% Load to 50% Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\75% Load to 50% Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\75% Load to 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\75% Load to 50% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Load|Vin Nominal|100% Load to 50% Load
* PROGRESS : 48 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\100% Load to 50% Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\100% Load to 50% Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\100% Load to 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\100% Load to 50% Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Step Load|Vin Nominal|100% Load to 75% Load
* PROGRESS : 49 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\100% Load to 75% Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\100% Load to 75% Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\100% Load to 75% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\100% Load to 75% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Nominal|100% Load to Light Load
* PROGRESS : 50 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\100% Load to Light Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\100% Load to Light Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\100% Load to Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\100% Load to Light Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Step Load|Vin Nominal|100% Load to No Load
* PROGRESS : 51 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Nominal\100% Load to No Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\100% Load to No Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\100% Load to No Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\100% Load to No Load\report.txt.html
* TEST TIME : 6 seconds
*
* TEST : Transient|Step Load|Vin Minimum|Light Load to 25% Load
* PROGRESS : 52 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\Light Load to 25% Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\Light Load to 25% Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\Light Load to 25% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\Light Load to 25% Load\report.txt.html
* TEST TIME : 6 seconds
*
* TEST : Transient|Step Load|Vin Minimum|Light Load to 50% Load
* PROGRESS : 53 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\Light Load to 50% Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\Light Load to 50% Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\Light Load to 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\Light Load to 50% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Minimum|Light Load to 100% Load
* PROGRESS : 54 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\Light Load to 100% Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\Light Load to 100% Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\Light Load to 100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\Light Load to 100% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Minimum|25% Load to Light Load
* PROGRESS : 55 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\25% Load to Light Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\25% Load to Light Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\25% Load to Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\25% Load to Light Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Step Load|Vin Minimum|25% Load to 50% Load
* PROGRESS : 56 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\25% Load to 50% Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\25% Load to 50% Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\25% Load to 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\25% Load to 50% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Load|Vin Minimum|50% Load to Light Load
* PROGRESS : 57 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\50% Load to Light Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\50% Load to Light Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\50% Load to Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\50% Load to Light Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Minimum|50% Load to 25% Load
* PROGRESS : 58 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\50% Load to 25% Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\50% Load to 25% Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\50% Load to 25% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\50% Load to 25% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Minimum|50% Load to 75% Load
* PROGRESS : 59 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\50% Load to 75% Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\50% Load to 75% Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\50% Load to 75% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\50% Load to 75% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Load|Vin Minimum|50% Load to 100% Load
* PROGRESS : 60 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\50% Load to 100% Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\50% Load to 100% Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\50% Load to 100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\50% Load to 100% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Load|Vin Minimum|75% Load to 100% Load
* PROGRESS : 61 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\75% Load to 100% Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\75% Load to 100% Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\75% Load to 100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\75% Load to 100% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Load|Vin Minimum|75% Load to 50% Load
* PROGRESS : 62 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\75% Load to 50% Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\75% Load to 50% Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\75% Load to 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\75% Load to 50% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Load|Vin Minimum|100% Load to 50% Load
* PROGRESS : 63 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\100% Load to 50% Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\100% Load to 50% Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\100% Load to 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\100% Load to 50% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Minimum|100% Load to 75% Load
* PROGRESS : 64 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\100% Load to 75% Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\100% Load to 75% Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\100% Load to 75% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\100% Load to 75% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Minimum|100% Load to Light Load
* PROGRESS : 65 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\100% Load to Light Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\100% Load to Light Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\100% Load to Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\100% Load to Light Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Step Load|Vin Minimum|100% Load to No Load
* PROGRESS : 66 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Minimum\100% Load to No Load/report.txt
* DECK : Transient\Step Load\Vin Minimum\100% Load to No Load\input.deck
* INIT : Transient\Step Load\Vin Minimum\100% Load to No Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Minimum\100% Load to No Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Maximum|Light Load to 25% Load
* PROGRESS : 67 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\Light Load to 25% Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\Light Load to 25% Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\Light Load to 25% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\Light Load to 25% Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Step Load|Vin Maximum|Light Load to 50% Load
* PROGRESS : 68 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\Light Load to 50% Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\Light Load to 50% Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\Light Load to 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\Light Load to 50% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Maximum|Light Load to 100% Load
* PROGRESS : 69 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\Light Load to 100% Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\Light Load to 100% Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\Light Load to 100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\Light Load to 100% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Maximum|25% Load to Light Load
* PROGRESS : 70 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\25% Load to Light Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\25% Load to Light Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\25% Load to Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\25% Load to Light Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Step Load|Vin Maximum|25% Load to 50% Load
* PROGRESS : 71 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\25% Load to 50% Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\25% Load to 50% Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\25% Load to 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\25% Load to 50% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Load|Vin Maximum|50% Load to Light Load
* PROGRESS : 72 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\50% Load to Light Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\50% Load to Light Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\50% Load to Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\50% Load to Light Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Maximum|50% Load to 25% Load
* PROGRESS : 73 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\50% Load to 25% Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\50% Load to 25% Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\50% Load to 25% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\50% Load to 25% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Maximum|50% Load to 75% Load
* PROGRESS : 74 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\50% Load to 75% Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\50% Load to 75% Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\50% Load to 75% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\50% Load to 75% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Maximum|50% Load to 100% Load
* PROGRESS : 75 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\50% Load to 100% Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\50% Load to 100% Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\50% Load to 100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\50% Load to 100% Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Step Load|Vin Maximum|75% Load to 100% Load
* PROGRESS : 76 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\75% Load to 100% Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\75% Load to 100% Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\75% Load to 100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\75% Load to 100% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Load|Vin Maximum|75% Load to 50% Load
* PROGRESS : 77 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\75% Load to 50% Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\75% Load to 50% Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\75% Load to 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\75% Load to 50% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Load|Vin Maximum|100% Load to 50% Load
* PROGRESS : 78 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\100% Load to 50% Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\100% Load to 50% Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\100% Load to 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\100% Load to 50% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Maximum|100% Load to 75% Load
* PROGRESS : 79 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\100% Load to 75% Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\100% Load to 75% Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\100% Load to 75% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\100% Load to 75% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Load|Vin Maximum|100% Load to Light Load
* PROGRESS : 80 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\100% Load to Light Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\100% Load to Light Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\100% Load to Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\100% Load to Light Load\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Step Load|Vin Maximum|100% Load to No Load
* PROGRESS : 81 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Load\Vin Maximum\100% Load to No Load/report.txt
* DECK : Transient\Step Load\Vin Maximum\100% Load to No Load\input.deck
* INIT : Transient\Step Load\Vin Maximum\100% Load to No Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Maximum\100% Load to No Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Line|Light Load|Vin Minimum to Vin Nominal
* PROGRESS : 82 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Line\Light Load\Vin Minimum to Vin Nominal/report.txt
* DECK : Transient\Step Line\Light Load\Vin Minimum to Vin Nominal\input.deck
* INIT : Transient\Step Line\Light Load\Vin Minimum to Vin Nominal\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Step Line\Light Load\Vin Minimum to Vin Nominal\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Line|Light Load|Vin Minimum to Vin Maximum
* PROGRESS : 83 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Line\Light Load\Vin Minimum to Vin Maximum/report.txt
* DECK : Transient\Step Line\Light Load\Vin Minimum to Vin Maximum\input.deck
* INIT : Transient\Step Line\Light Load\Vin Minimum to Vin Maximum\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Step Line\Light Load\Vin Minimum to Vin Maximum\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Line|Light Load|Vin Maximum to Vin Nominal
* PROGRESS : 84 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Line\Light Load\Vin Maximum to Vin Nominal/report.txt
* DECK : Transient\Step Line\Light Load\Vin Maximum to Vin Nominal\input.deck
* INIT : Transient\Step Line\Light Load\Vin Maximum to Vin Nominal\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Step Line\Light Load\Vin Maximum to Vin Nominal\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Line|Light Load|Vin Maximum to Vin Minimum
* PROGRESS : 85 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Line\Light Load\Vin Maximum to Vin Minimum/report.txt
* DECK : Transient\Step Line\Light Load\Vin Maximum to Vin Minimum\input.deck
* INIT : Transient\Step Line\Light Load\Vin Maximum to Vin Minimum\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Step Line\Light Load\Vin Maximum to Vin Minimum\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Line|50% Load|Vin Minimum to Vin Nominal
* PROGRESS : 86 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Line\50% Load\Vin Minimum to Vin Nominal/report.txt
* DECK : Transient\Step Line\50% Load\Vin Minimum to Vin Nominal\input.deck
* INIT : Transient\Step Line\50% Load\Vin Minimum to Vin Nominal\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Step Line\50% Load\Vin Minimum to Vin Nominal\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Line|50% Load|Vin Minimum to Vin Maximum
* PROGRESS : 87 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Line\50% Load\Vin Minimum to Vin Maximum/report.txt
* DECK : Transient\Step Line\50% Load\Vin Minimum to Vin Maximum\input.deck
* INIT : Transient\Step Line\50% Load\Vin Minimum to Vin Maximum\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Step Line\50% Load\Vin Minimum to Vin Maximum\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Line|50% Load|Vin Maximum to Vin Nominal
* PROGRESS : 88 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Line\50% Load\Vin Maximum to Vin Nominal/report.txt
* DECK : Transient\Step Line\50% Load\Vin Maximum to Vin Nominal\input.deck
* INIT : Transient\Step Line\50% Load\Vin Maximum to Vin Nominal\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Step Line\50% Load\Vin Maximum to Vin Nominal\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Line|50% Load|Vin Maximum to Vin Minimum
* PROGRESS : 89 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Line\50% Load\Vin Maximum to Vin Minimum/report.txt
* DECK : Transient\Step Line\50% Load\Vin Maximum to Vin Minimum\input.deck
* INIT : Transient\Step Line\50% Load\Vin Maximum to Vin Minimum\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Step Line\50% Load\Vin Maximum to Vin Minimum\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Step Line|100% Load|Vin Minimum to Vin Nominal
* PROGRESS : 90 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Line\100% Load\Vin Minimum to Vin Nominal/report.txt
* DECK : Transient\Step Line\100% Load\Vin Minimum to Vin Nominal\input.deck
* INIT : Transient\Step Line\100% Load\Vin Minimum to Vin Nominal\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Step Line\100% Load\Vin Minimum to Vin Nominal\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Line|100% Load|Vin Minimum to Vin Maximum
* PROGRESS : 91 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Line\100% Load\Vin Minimum to Vin Maximum/report.txt
* DECK : Transient\Step Line\100% Load\Vin Minimum to Vin Maximum\input.deck
* INIT : Transient\Step Line\100% Load\Vin Minimum to Vin Maximum\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Step Line\100% Load\Vin Minimum to Vin Maximum\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Line|100% Load|Vin Maximum to Vin Nominal
* PROGRESS : 92 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Line\100% Load\Vin Maximum to Vin Nominal/report.txt
* DECK : Transient\Step Line\100% Load\Vin Maximum to Vin Nominal\input.deck
* INIT : Transient\Step Line\100% Load\Vin Maximum to Vin Nominal\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Step Line\100% Load\Vin Maximum to Vin Nominal\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Step Line|100% Load|Vin Maximum to Vin Minimum
* PROGRESS : 93 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Step Line\100% Load\Vin Maximum to Vin Minimum/report.txt
* DECK : Transient\Step Line\100% Load\Vin Maximum to Vin Minimum\input.deck
* INIT : Transient\Step Line\100% Load\Vin Maximum to Vin Minimum\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Step Line\100% Load\Vin Maximum to Vin Minimum\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Startup|Light Load|0V to Vin Minimum
* PROGRESS : 94 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Startup\Light Load\0V to Vin Minimum/report.txt
* DECK : Transient\Startup\Light Load\0V to Vin Minimum\input.deck
* INIT : Transient\Startup\Light Load\0V to Vin Minimum\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Startup\Light Load\0V to Vin Minimum\report.txt.html
* TEST TIME : 6 seconds
*
* TEST : Transient|Startup|Light Load|0V to Vin Nominal
* PROGRESS : 95 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Startup\Light Load\0V to Vin Nominal/report.txt
* DECK : Transient\Startup\Light Load\0V to Vin Nominal\input.deck
* INIT : Transient\Startup\Light Load\0V to Vin Nominal\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Startup\Light Load\0V to Vin Nominal\report.txt.html
* TEST TIME : 6 seconds
*
* TEST : Transient|Startup|Light Load|0V to Vin Maximum
* PROGRESS : 96 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Startup\Light Load\0V to Vin Maximum/report.txt
* DECK : Transient\Startup\Light Load\0V to Vin Maximum\input.deck
* INIT : Transient\Startup\Light Load\0V to Vin Maximum\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Startup\Light Load\0V to Vin Maximum\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Startup|50% Load|0V to Vin Minimum
* PROGRESS : 97 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Startup\50% Load\0V to Vin Minimum/report.txt
* DECK : Transient\Startup\50% Load\0V to Vin Minimum\input.deck
* INIT : Transient\Startup\50% Load\0V to Vin Minimum\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Startup\50% Load\0V to Vin Minimum\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Startup|50% Load|0V to Vin Nominal
* PROGRESS : 98 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Startup\50% Load\0V to Vin Nominal/report.txt
* DECK : Transient\Startup\50% Load\0V to Vin Nominal\input.deck
* INIT : Transient\Startup\50% Load\0V to Vin Nominal\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Startup\50% Load\0V to Vin Nominal\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Startup|50% Load|0V to Vin Maximum
* PROGRESS : 99 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Startup\50% Load\0V to Vin Maximum/report.txt
* DECK : Transient\Startup\50% Load\0V to Vin Maximum\input.deck
* INIT : Transient\Startup\50% Load\0V to Vin Maximum\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Startup\50% Load\0V to Vin Maximum\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Startup|100% Load|0V to Vin Minimum
* PROGRESS : 100 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Startup\100% Load\0V to Vin Minimum/report.txt
* DECK : Transient\Startup\100% Load\0V to Vin Minimum\input.deck
* INIT : Transient\Startup\100% Load\0V to Vin Minimum\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Startup\100% Load\0V to Vin Minimum\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Startup|100% Load|0V to Vin Nominal
* PROGRESS : 101 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Startup\100% Load\0V to Vin Nominal/report.txt
* DECK : Transient\Startup\100% Load\0V to Vin Nominal\input.deck
* INIT : Transient\Startup\100% Load\0V to Vin Nominal\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Startup\100% Load\0V to Vin Nominal\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Startup|100% Load|0V to Vin Maximum
* PROGRESS : 102 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Startup\100% Load\0V to Vin Maximum/report.txt
* DECK : Transient\Startup\100% Load\0V to Vin Maximum\input.deck
* INIT : Transient\Startup\100% Load\0V to Vin Maximum\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Startup\100% Load\0V to Vin Maximum\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Short Circuit|Vin Nominal|Light Load to Short Circuit
* PROGRESS : 103 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Nominal\Light Load to Short Circuit/report.txt
* DECK : Transient\Short Circuit\Vin Nominal\Light Load to Short Circuit\input.deck
* INIT : Transient\Short Circuit\Vin Nominal\Light Load to Short Circuit\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Short Circuit\Vin Nominal\Light Load to Short Circuit\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Short Circuit|Vin Nominal|50% Load to Short Circuit
* PROGRESS : 104 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Nominal\50% Load to Short Circuit/report.txt
* DECK : Transient\Short Circuit\Vin Nominal\50% Load to Short Circuit\input.deck
* INIT : Transient\Short Circuit\Vin Nominal\50% Load to Short Circuit\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Short Circuit\Vin Nominal\50% Load to Short Circuit\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Short Circuit|Vin Nominal|100% Load to Short Circuit
* PROGRESS : 105 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Nominal\100% Load to Short Circuit/report.txt
* DECK : Transient\Short Circuit\Vin Nominal\100% Load to Short Circuit\input.deck
* INIT : Transient\Short Circuit\Vin Nominal\100% Load to Short Circuit\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Short Circuit\Vin Nominal\100% Load to Short Circuit\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Short Circuit|Vin Minimum|Light Load to Short Circuit
* PROGRESS : 106 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Minimum\Light Load to Short Circuit/report.txt
* DECK : Transient\Short Circuit\Vin Minimum\Light Load to Short Circuit\input.deck
* INIT : Transient\Short Circuit\Vin Minimum\Light Load to Short Circuit\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Short Circuit\Vin Minimum\Light Load to Short Circuit\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Short Circuit|Vin Minimum|50% Load to Short Circuit
* PROGRESS : 107 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Minimum\50% Load to Short Circuit/report.txt
* DECK : Transient\Short Circuit\Vin Minimum\50% Load to Short Circuit\input.deck
* INIT : Transient\Short Circuit\Vin Minimum\50% Load to Short Circuit\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Short Circuit\Vin Minimum\50% Load to Short Circuit\report.txt.html
* TEST TIME : 7 seconds
*
* TEST : Transient|Short Circuit|Vin Minimum|100% Load to Short Circuit
* PROGRESS : 108 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Minimum\100% Load to Short Circuit/report.txt
* DECK : Transient\Short Circuit\Vin Minimum\100% Load to Short Circuit\input.deck
* INIT : Transient\Short Circuit\Vin Minimum\100% Load to Short Circuit\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Short Circuit\Vin Minimum\100% Load to Short Circuit\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Short Circuit|Vin Maximum|Light Load to Short Circuit
* PROGRESS : 109 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Maximum\Light Load to Short Circuit/report.txt
* DECK : Transient\Short Circuit\Vin Maximum\Light Load to Short Circuit\input.deck
* INIT : Transient\Short Circuit\Vin Maximum\Light Load to Short Circuit\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Short Circuit\Vin Maximum\Light Load to Short Circuit\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Transient|Short Circuit|Vin Maximum|50% Load to Short Circuit
* PROGRESS : 110 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Maximum\50% Load to Short Circuit/report.txt
* DECK : Transient\Short Circuit\Vin Maximum\50% Load to Short Circuit\input.deck
* INIT : Transient\Short Circuit\Vin Maximum\50% Load to Short Circuit\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Short Circuit\Vin Maximum\50% Load to Short Circuit\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Short Circuit|Vin Maximum|100% Load to Short Circuit
* PROGRESS : 111 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Maximum\100% Load to Short Circuit/report.txt
* DECK : Transient\Short Circuit\Vin Maximum\100% Load to Short Circuit\input.deck
* INIT : Transient\Short Circuit\Vin Maximum\100% Load to Short Circuit\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Short Circuit\Vin Maximum\100% Load to Short Circuit\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Transient|Short Circuit|Vin Nominal|Light Load to Short Circuit and Recover
* PROGRESS : 112 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Nominal\Light Load to Short Circuit and Recover/report.txt
* DECK : Transient\Short Circuit\Vin Nominal\Light Load to Short Circuit and Recover\input.deck
* INIT : Transient\Short Circuit\Vin Nominal\Light Load to Short Circuit and Recover\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Short Circuit\Vin Nominal\Light Load to Short Circuit and Recover\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Short Circuit|Vin Nominal|50% Load to Short Circuit and Recover
* PROGRESS : 113 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Nominal\50% Load to Short Circuit and Recover/report.txt
* DECK : Transient\Short Circuit\Vin Nominal\50% Load to Short Circuit and Recover\input.deck
* INIT : Transient\Short Circuit\Vin Nominal\50% Load to Short Circuit and Recover\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Short Circuit\Vin Nominal\50% Load to Short Circuit and Recover\report.txt.html
* TEST TIME : 6 seconds
*
* TEST : Transient|Short Circuit|Vin Nominal|100% Load to Short Circuit and Recover
* PROGRESS : 114 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Nominal\100% Load to Short Circuit and Recover/report.txt
* DECK : Transient\Short Circuit\Vin Nominal\100% Load to Short Circuit and Recover\input.deck
* INIT : Transient\Short Circuit\Vin Nominal\100% Load to Short Circuit and Recover\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Short Circuit\Vin Nominal\100% Load to Short Circuit and Recover\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Short Circuit|Vin Minimum|Light Load to Short Circuit and Recover
* PROGRESS : 115 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Minimum\Light Load to Short Circuit and Recover/report.txt
* DECK : Transient\Short Circuit\Vin Minimum\Light Load to Short Circuit and Recover\input.deck
* INIT : Transient\Short Circuit\Vin Minimum\Light Load to Short Circuit and Recover\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Short Circuit\Vin Minimum\Light Load to Short Circuit and Recover\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Short Circuit|Vin Minimum|50% Load to Short Circuit and Recover
* PROGRESS : 116 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Minimum\50% Load to Short Circuit and Recover/report.txt
* DECK : Transient\Short Circuit\Vin Minimum\50% Load to Short Circuit and Recover\input.deck
* INIT : Transient\Short Circuit\Vin Minimum\50% Load to Short Circuit and Recover\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Short Circuit\Vin Minimum\50% Load to Short Circuit and Recover\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Short Circuit|Vin Minimum|100% Load to Short Circuit and Recover
* PROGRESS : 117 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Minimum\100% Load to Short Circuit and Recover/report.txt
* DECK : Transient\Short Circuit\Vin Minimum\100% Load to Short Circuit and Recover\input.deck
* INIT : Transient\Short Circuit\Vin Minimum\100% Load to Short Circuit and Recover\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Short Circuit\Vin Minimum\100% Load to Short Circuit and Recover\report.txt.html
* TEST TIME : 5 seconds
*
* TEST : Transient|Short Circuit|Vin Maximum|Light Load to Short Circuit and Recover
* PROGRESS : 118 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Maximum\Light Load to Short Circuit and Recover/report.txt
* DECK : Transient\Short Circuit\Vin Maximum\Light Load to Short Circuit and Recover\input.deck
* INIT : Transient\Short Circuit\Vin Maximum\Light Load to Short Circuit and Recover\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Short Circuit\Vin Maximum\Light Load to Short Circuit and Recover\report.txt.html
* TEST TIME : 6 seconds
*
* TEST : Transient|Short Circuit|Vin Maximum|50% Load to Short Circuit and Recover
* PROGRESS : 119 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Maximum\50% Load to Short Circuit and Recover/report.txt
* DECK : Transient\Short Circuit\Vin Maximum\50% Load to Short Circuit and Recover\input.deck
* INIT : Transient\Short Circuit\Vin Maximum\50% Load to Short Circuit and Recover\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Short Circuit\Vin Maximum\50% Load to Short Circuit and Recover\report.txt.html
* TEST TIME : 6 seconds
*
* TEST : Transient|Short Circuit|Vin Maximum|100% Load to Short Circuit and Recover
* PROGRESS : 120 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Transient\Short Circuit\Vin Maximum\100% Load to Short Circuit and Recover/report.txt
* DECK : Transient\Short Circuit\Vin Maximum\100% Load to Short Circuit and Recover\input.deck
* INIT : Transient\Short Circuit\Vin Maximum\100% Load to Short Circuit and Recover\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Short Circuit\Vin Maximum\100% Load to Short Circuit and Recover\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|Light Load
* PROGRESS : 121 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Steady-State\Steady-State\Vin Nominal\Light Load/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\Light Load\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\Light Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|50% Load
* PROGRESS : 122 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Steady-State\Steady-State\Vin Nominal\50% Load/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\50% Load\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\50% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|100% Load
* PROGRESS : 123 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Steady-State\Steady-State\Vin Nominal\100% Load/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\100% Load\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\100% Load\report.txt.html
* TEST TIME : 4 seconds
*
* TEST : Steady-State|Steady-State|Vin Minimum|Light Load
* PROGRESS : 124 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Steady-State\Steady-State\Vin Minimum\Light Load/report.txt
* DECK : Steady-State\Steady-State\Vin Minimum\Light Load\input.deck
* INIT : Steady-State\Steady-State\Vin Minimum\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Minimum\Light Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Steady-State|Steady-State|Vin Minimum|50% Load
* PROGRESS : 125 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Steady-State\Steady-State\Vin Minimum\50% Load/report.txt
* DECK : Steady-State\Steady-State\Vin Minimum\50% Load\input.deck
* INIT : Steady-State\Steady-State\Vin Minimum\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Minimum\50% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Steady-State|Steady-State|Vin Minimum|100% Load
* PROGRESS : 126 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Steady-State\Steady-State\Vin Minimum\100% Load/report.txt
* DECK : Steady-State\Steady-State\Vin Minimum\100% Load\input.deck
* INIT : Steady-State\Steady-State\Vin Minimum\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Minimum\100% Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Steady-State|Steady-State|Vin Maximum|Light Load
* PROGRESS : 127 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Steady-State\Steady-State\Vin Maximum\Light Load/report.txt
* DECK : Steady-State\Steady-State\Vin Maximum\Light Load\input.deck
* INIT : Steady-State\Steady-State\Vin Maximum\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Maximum\Light Load\report.txt.html
* TEST TIME : 3 seconds
*
* TEST : Steady-State|Steady-State|Vin Maximum|50% Load
* PROGRESS : 128 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Steady-State\Steady-State\Vin Maximum\50% Load/report.txt
* DECK : Steady-State\Steady-State\Vin Maximum\50% Load\input.deck
* INIT : Steady-State\Steady-State\Vin Maximum\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Maximum\50% Load\report.txt.html
* TEST TIME : 2 seconds
*
* TEST : Steady-State|Steady-State|Vin Maximum|100% Load
* PROGRESS : 129 of 129
* SIMULATOR : simplis
* LOG : D:\data\projects\simplistechnologies.com\dvm\syncbuck\schematic\LTC3406B\Test Ckts\DVM_REPORTS\2011-05-23-15_12_01_PM\Steady-State\Steady-State\Vin Maximum\100% Load/report.txt
* DECK : Steady-State\Steady-State\Vin Maximum\100% Load\input.deck
* INIT : Steady-State\Steady-State\Vin Maximum\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Maximum\100% Load\report.txt.html
* TEST TIME : 3 seconds
*
*
* TOTAL TIME: 724 seconds
* TESTS RUN : 129 of 129