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» DVM Test Report: Efficiency and Loop Characterization|Vin Maximum|50% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Maximum|50% Load
Date / Time 5/3/2013 4:32:31 PM
Report Directory DVM_REPORTS\2013-05-03-4_27_35_PM\Efficiency and Loop Characterization\Vin Maximum\50% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.8681%
Frequency(CLK) 95.409431kHertz
Power(LOAD) 60.491
Power(SRC) 63.0982
eta_max 95.8681%
gain_crossover_freq 4.44166k
gain_margin 26.0284
gmargin_max 26.0284
gxover_max 4.44166k
iload_max 2.51046
min_phase 73.1077
phase_crossover_freq 31.5046k
min_phase_freq 4.44166k
phase_margin 73.0652
pmargin_max 73.0652
sw_freq_max 95.409431kHertz
ICout
AVG
4.79316u
MIN
-2.50787
MAX
1.4107
RMS
1.20358
IDQ1
AVG
157.779m
MIN
-598.414m
MAX
739.219m
RMS
365.568m
IDQ2
AVG
157.739m
MIN
-599.096m
MAX
739.283m
RMS
365.54m
ILOAD
AVG
2.51046
MIN
2.50786
MAX
2.51194
RMS
2.51046
ISRC
AVG
157.779m
MIN
-598.414m
MAX
739.219m
RMS
365.568m
Im
AVG
-80.1394u
MIN
-490.115m
MAX
489.955m
RMS
283.205m
Ip
AVG
120.136u
MIN
-522.72m
MAX
523.021m
RMS
371.283m
Ir
AVG
39.9969u
MIN
-739.279m
MAX
739.215m
RMS
518.375m
Is1
AVG
1.25568
MIN
-5.06917u
MAX
3.92265
RMS
1.96967
Is2
AVG
1.25478
MIN
-5.06919u
MAX
3.92039
RMS
1.96838
VLOAD
AVG
24.0956
MIN
24.0707
MAX
24.1097
RMS
24.0956
VSRC
AVG
399.984
MIN
399.926
MAX
400.06
RMS
399.984
VSW
AVG
199.984
MIN
-725.096m
MAX
400.783
RMS
282.308
Vs
AVG
-50.2093m
MIN
-25.0463
MAX
24.8895
RMS
24.8857
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.1097) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0707) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (26.0284) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (73.0652) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac68_4469.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop68_4446.sxgph
SRC
ISRC
VSRC
SXGPH File simplis_pop68_4436.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop68_4416.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop68_4441.sxgph
Other SXGPH Files
DVM Bode Plot Input#log#ac simplis_ac68_4476.sxgph
default#4424#pop simplis_pop68_4424.sxgph
Modulator#pop simplis_pop68_4429.sxgph