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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|15% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Nominal|15% Load
Date / Time 5/3/2013 4:28:08 PM
Report Directory DVM_REPORTS\2013-05-03-4_27_35_PM\Efficiency and Loop Characterization\Vin Nominal\15% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.6321%
Frequency(CLK) 88.363904kHertz
Power(LOAD) 18.1572
Power(SRC) 18.9865
eta_nom 95.6321%
gain_crossover_freq 3.39574k
gain_margin 28.0994
gmargin_nom 28.0994
gxover_nom 3.39574k
iload_nom 753.507m
min_phase 84.9521
phase_crossover_freq 35.2226k
min_phase_freq 3.39574k
phase_margin 84.9484
pmargin_nom 84.9484
sw_freq_nom 88.363904kHertz
ICout
AVG
4.81619u
MIN
-753.275m
MAX
775.88m
RMS
566.3m
IDQ1
AVG
49.9822m
MIN
-522.863m
MAX
552.502m
RMS
259.16m
IDQ2
AVG
49.9442m
MIN
-527.127m
MAX
546.607m
RMS
259.159m
ILOAD
AVG
753.507m
MIN
753.266m
MAX
753.756m
RMS
753.507m
ISRC
AVG
49.9822m
MIN
-522.863m
MAX
552.502m
RMS
259.16m
Im
AVG
-21.5526u
MIN
-521.495m
MAX
521.421m
RMS
304.241m
Ip
AVG
59.5516u
MIN
-203.781m
MAX
203.953m
RMS
125.694m
Ir
AVG
37.999u
MIN
-522.552m
MAX
522.407m
RMS
367.933m
Is1
AVG
376.979m
MIN
-5.05129u
MAX
1.52964
RMS
666.93m
Is2
AVG
376.532m
MIN
-5.0513u
MAX
1.52835
RMS
666.252m
VLOAD
AVG
24.0969
MIN
24.0894
MAX
24.1047
RMS
24.0969
VSRC
AVG
379.995
MIN
379.945
MAX
380.052
RMS
379.995
VSW
AVG
189.995
MIN
-723.804m
MAX
380.775
RMS
268.282
Vs
AVG
-15.0664m
MIN
-24.8778
MAX
24.8167
RMS
24.5717
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.1047) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0894) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (28.0994) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (84.9484) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac48_3169.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop48_3146.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop48_3136.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop48_3116.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop48_3141.sxgph
Other SXGPH Files
DVM Bode Plot Input#log#ac simplis_ac48_3176.sxgph
default#3124#pop simplis_pop48_3124.sxgph
Modulator#pop simplis_pop48_3129.sxgph