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» DVM Test Report: Efficiency and Loop Characterization|Vin Maximum|80% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Maximum|80% Load
Date / Time 5/3/2013 4:33:11 PM
Report Directory DVM_REPORTS\2013-05-03-4_27_35_PM\Efficiency and Loop Characterization\Vin Maximum\80% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.4958%
Frequency(CLK) 93.621368kHertz
Power(LOAD) 96.7578
Power(SRC) 101.322
eta_max 95.4958%
gain_crossover_freq 5.44648k
gain_margin 21.1075
gmargin_max 21.1075
gxover_max 5.44648k
iload_max 4.016
min_phase 57.2504
phase_crossover_freq 23.8124k
min_phase_freq 5.44648k
phase_margin 57.2344
pmargin_max 57.2344
sw_freq_max 93.621368kHertz
ICout
AVG
4.78842u
MIN
-4.00936
MAX
2.10366
RMS
1.8211
IDQ1
AVG
253.365m
MIN
-697.212m
MAX
981.234m
RMS
495.569m
IDQ2
AVG
253.325m
MIN
-696.975m
MAX
981.256m
RMS
495.531m
ILOAD
AVG
4.016
MIN
4.00935
MAX
4.01953
RMS
4.01601
ISRC
AVG
253.365m
MIN
-697.212m
MAX
981.234m
RMS
495.569m
Im
AVG
-89.1178u
MIN
-500.665m
MAX
500.486m
RMS
289.439m
Ip
AVG
129.113u
MIN
-816.094m
MAX
816.427m
RMS
588.118m
Ir
AVG
39.9949u
MIN
-981.252m
MAX
981.23m
RMS
701.984m
Is1
AVG
2.00849
MIN
-5.08205u
MAX
6.1232
RMS
3.11967
Is2
AVG
2.00752
MIN
-5.08207u
MAX
6.1207
RMS
3.11826
VLOAD
AVG
24.093
MIN
24.0532
MAX
24.1141
RMS
24.0931
VSRC
AVG
399.975
MIN
399.902
MAX
400.07
RMS
399.975
VSW
AVG
199.975
MIN
-731.989m
MAX
400.8
RMS
282.239
Vs
AVG
-80.3202m
MIN
-25.1668
MAX
24.922
RMS
24.9448
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.1141) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0532) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (21.1075) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (57.2344) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac71_4664.sxgph
LOAD
ILOAD
VLOAD
SXGPH File simplis_pop71_4641.sxgph
SRC
ISRC
VSRC
SXGPH File simplis_pop71_4631.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop71_4611.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop71_4636.sxgph
Other SXGPH Files
DVM Bode Plot Input#log#ac simplis_ac71_4671.sxgph
default#4619#pop simplis_pop71_4619.sxgph
Modulator#pop simplis_pop71_4624.sxgph