DVM - Design Verification Module

SteadyState() Test Objective

The purpose of the SteadyState(0 test is to measure the steady-state operating point of the converter. The input is configured as a DC Input Source, and the output is configured as a Resistive Load. Since the test objective does not specify the input voltage nor the output current, you must provide these values in the Source and Load columns in the testplan.

Only a POP analysis is used in the SteadyState() test with the directives taken from the POP tab, which is shown below and accessed from the Full Power Assist DVM control symbol.

The test report includes frequency, source, and load graphs as well as the following scalar values which are defined in the Measured Scalar Values section below:

Efficiency
Power({load_name})
Power({source_name})
sw_freq

In this Topic ShowHide

Testplan Syntax
Source and Load Subcircuit Configuration
Measured Scalar Values
Measured Specification Values
Testplan Example
Test Report

Testplan Syntax

The SteadyState() objective has no arguments. In the Objective column of the testplan, you simply enter:

SteadyState

Source and Load Subcircuit Configuration

The SteadyState() test objective sets the source and load subcircuits to the following:

Source	Load
DC Input Source	Resistive Load

Loads other than the output under test are set to the Resistive Load. All other sources are set to the DC Input Source.

Measured Scalar Values

The SteadyState() test objective measures the following scalar values:

Scalar Name	Description
Efficiency	The overall efficiency of the converter taken from the POP simulation
Power({load_name)	The power of each input source taken from the POP simulation
Power({load_name})	The power of each output load taken from the POP simulation
sw_freq	A number which represents the converter switching frequency

Measured Specification Values

In the following table, {load_name} is the name assigned to each load. The default value is LOAD. DVM forces each load name to be unique so that the scalar and specification values for each load are unique.

Specification Name	PASS/FAIL Criteria
Min_V{load_name}	The minimum value of the output voltage during the simulation time is greater that the minimum specification value.
Max_V{load_name}	The maximum value of the output during the simulation time is less than the maximum specification value.

Testplan Example

The SteadyState() test objective is used in several built-in testplans. Shown below is a test from the DC/DC 1 input/1 output testplan. The source and load are defined in the Full Power Assist DVM control symbol. The test configures the source to use the Nominal symbolic value from the Input tab and configures the load based on the Light symbolic value from the Output tab.

*?@ Analysis	Objective	Source	Load	Label
Steady-State	SteadyState	SOURCE(INPUT:1, Nominal)	LOAD(OUTPUT:1, Light)	Steady-State\|Steady-State\|Vin Nominal\|Light Load

Test Report

You can view the complete test report in a new browser window here: SteadyState() Test Report. Below is an interactive link to the same test report.