DVM - Design Verification Module

DC/DC Test Objectives

Using the built-in testplans, the DVM module enables you to automatically run a suite of common tests to check the design against your specifications. When starting from a good working schematic, you need to replace only the input source and output load values and add a DVM control symbol which you then use to specify the input voltage, output current ranges, switching frequency, etc. After you enter these specifications, you can immediately start verifying the design using the built-in testplans.

The DC/DC test objectives can be combined with the following types of analyses:

AC Analysis

The test objectives for AC analysis are the following:

Objective	Description
BodePlot()	Measures control-loop stability. Configures the input a DC Input Source and the output as a special BodePlot Load with a small-signal AC source and a Bode Plot probe.
Impedance()	Measures either the converter input or output impedance depending on whether the reference designator is a DVM source or load. If the reference designator is a source, input is configured as a DC Input Impedance Source and the output as a Resistive Load. If the reference designator is a load, input is configured as a DC Input Source and the output as an Impedance Load.
ConductedSusceptibility()	Determines the converter's ability to reject a small-signal perturbation at the input and automatically connects a special susceptibility probe between the input source and each managed DVM load. Configures the input as a DC Input Susceptibility Source and the output as a Resistive Load.
No Simulation	Does not run a simulation during the test; used to run PreProcess or PostProcess scripts.

Transient Analysis

The test objectives for DC/DC transient analysis are the following:

Objective	Description
StepLoad()	Verifies that the output voltage is within regulation when the load current is ramped between initial and final current values. Configures the input as a DC Input Source and the output as a Ramp Load.
StepLine()	Verifies that the output voltage is within regulation when the line voltage is ramped between initial and final voltage values. Configures the input as a Ramp Input Source and the output as a Resistive Load.
PulseLoad()	Similar to the StepLoad() test objective except that the load current is a pulse. Configures the input as a DC Input Source and the output as a Pulse Load and then runs a POP and a transient simulation.
PulseLine()	Similar to the StepLine() test objective except that the line voltage is a pulse. Configures the input as a Pulse Input Source and the output as a Resistive Load and then runs a POP and a transient simulation.
Startup()	Determines the converter response to a startup. Configures the input as a Ramp Input Source and the output as a Resistive Load and then runs a transient simulation.
ShortCkt()	Examines the behavior of the converter during a short-circuit event. Configures the input as a DC Input Source and the output as a Short Circuit Load and then runs a POP and a transient simulation.
NoSimulation	Does not run a simulation during the test; used to run PreProcess or PostProcess scripts.

Steady-State Analysis

The test objectives for steady-state analysis are in the following table.

Objective	Description
SteadyState()	Measures the steady-state operating point of the converter. Configures the input as a DC Input Source and the output as a Resistive Load and then runs a POP analysis to bring the converter to a steady state.
No Simulation	Does not run a simulation during the test; used to run PreProcess or PostProcess scripts.